This invention relates to solid state integrated circuit construction and is more particularly directed to three-dimensional, epitaxially-grown vertical devices, i.e., multilayer semiconductor devices in which semiconductor, conductor and insulator layers are epitaxially grown or deposited one atop another on a substrate.
A vertical integrated circuit is typically formed of a number of alternate layers of semiconductor, metal (e.g. aluminum), and insulator (e.g. oxide). The metal and semiconductor at different levels are interconnected by means of metallic deposits that fill in grooves or bores etched through the multiple layers. Conventional methods of carrying out so-called three-dimensional integration are described, e.g. in U.S. Pats. Nos. 3,613,226; 4,335,161; 4,448,632; 4,596,604; 4,479,297; 4,489,478; and 4,467,518. In each of these, at least some of the layers are amorphous or polycrystalline. Consequently, there is no matching of the crystal lattice structure from one layer to the next. As a result, it is difficult to stack devices such as FETs more than two deep. Consequently, there has been only limited success in building true three-dimensional integrated circuits. Accordingly, for multiple level structures, it has been necessary to make integrated circuits on several wafers, stack the wafers one on top of another, and then connect vias for interconnection through the wafers. This is a complex and time consuming procedure, involving many different materials.
A number of elements or combinations of elements form a cubic zinc blende lattice structure, which is structurally similar to the diamond cubic structure of silicon and germanium. A number of "zinc blende" crystals include, in addition to ZnS, a number of semiconductor materials such as InP, InSb, InAs, GaAs, and others of the III-V type, as well as a number of crystals such as ZnSe, CdS, CdSe, and CdTe of the II-VI type. Each of these has its own characteristic lattice constant a. There are other crystals of similar structure, such as CuF, AgI, etc. made of elements of families outside the II-VI and III-V groups. SiC is an example of a IV--IV type. The electrical properties of these crystalline materials vary from one to the next, with some such as InSb being somewhat metallic at room temperature, others such as GaAs being semiconductors or semi-insulators, and still others such as CdTe being insulators or dielectrics. Each material has a characteristic band gap, which is known. Generally, the group III elements include Al, Ga, In, and Tl, and the type V elements include P, As, Sb, and Bi. The group II elements include Zn, Cd, and Hg, while group VI elements include S, Se, Te and Po. A type III-V material has one element selected from group III and another selected from Group V, while a type II-VI material has one element selected from group II and another selected from group VI.
It has long been desired to construct multi circuit layered vertical devices, which would have the advantage of having multiple devices in the same unit of substrate area now occupied by a single conventional device Because the devices are positioned close to one another in the vertical dimension it is also possible to reduce the power and the time required for transferring a bit of data from one to the next. Memory can be included in some of the layers Multi-circuit layer architecture is highly suited for large-scale parallel information processing.
However, conventional techniques employ a single-crystal substrate, metal conductors (Al or Au, for example), and oxide insulators (typically SiO.sub.2 or GeO.sub.2), so there are at least some amorphous or polycrystalline layers. There is no reliable way to grow a single-crystal semiconductor layer on a polycrystalline layer. Also, the lattice constant should be fairly closely matched from one layer to the next to obtain growth of mono-crystalline layers. However, this is typically not the case, especially for silicon and quartz, which have quite different crystal structure and different lattice constants. Consequently, stacked devices have been limited to about two active elements per stack, and have had to employ polycrystalline silicon for device construction.